Logic ICs

This page is an overview of the 74-series and CD4000-series digital logic chips in de:volt, organised by function: gates, arithmetic, counters, registers / flip-flops / shift registers, decoders and multiplexers, and memory. Each one is a standard DIP package whose pin map matches the real part, so a circuit you build here transfers straight to a breadboard.

de:volt simulates these as committed logic — the engine evaluates each chip’s truth table or state machine directly rather than solving every internal transistor. That makes them fast and exact, but it also means you should treat the published pinout as the contract: wire the pins the catalog lists, and don’t expect undocumented internal nodes to exist.

Logic families and supply rails

Three families are represented, and they differ mostly in supply range and input thresholds:

LS-TTL parts want a clean 5 V rail. HC-CMOS and CMOS-4000 parts tolerate a wide supply, and their thresholds scale with it (roughly 30% / 70% of VCC). On every chip, VCC sits at one corner and GND at the diagonally opposite corner, and the DIP straddles the centre gap of the breadboard. Add a 100 nF decoupling capacitor across VCC and GND, close to the chip.

Never leave a CMOS input floating. Tie every unused input HIGH (VCC) or LOW (GND). A floating LS-TTL input usually drifts toward a logic HIGH, but relying on that is bad practice — tie unused inputs deliberately on every family.

Part index

Gates

The five 74LS gate chips each pack four (or, for the inverter, six) identical gates into a 14-pin DIP. The two-input parts share a layout: gate n’s inputs are nA/nB and its output is nY. The 74LS00 is NAND, 74LS08 AND, 74LS32 OR, 74LS86 XOR, and the 74LS04 is six inverters (nA → nY). All are LS-TTL on a 5 V rail. The 74LS86 is the workhorse of parity generators and the sum term inside adders.

The 74HC14 is a hex inverter with a twist: each input is a Schmitt trigger. Instead of one switching point it has two — at 5 V the output trips LOW once the input climbs past V_T+ ≈ 2.7 V and only goes HIGH again once it falls below V_T- ≈ 1.6 V. That gap (hysteresis) cleans up slow or noisy edges, so it’s the part to reach for when squaring up a sensor signal, debouncing, or building a simple RC relaxation oscillator. The thresholds scale with the supply.

Arithmetic

The 74LS283 is a 4-bit binary full adder with look-ahead (fast) carry in a 16-pin DIP. It adds two 4-bit words A1–A4 and B1–B4 plus a carry-in C0, producing the sum S1–S4 and a carry-out C4. Chain the C4 of one chip into the C0 of the next to add 8-, 12-, or 16-bit words. Pair it with a 74LS86 and you have the classic adder/subtractor building block.

Counters

The 74LS161 is a 4-bit synchronous binary counter (0–15). All flip-flops clock together off CLK, so the outputs QA–QD change cleanly with no ripple. For free-running counting, tie /CLR, /LOAD, ENP, and ENT HIGH and feed a clock (a 555 astable or the clock generator). RCO pulses at terminal count to cascade into the next stage. /LOAD is synchronous (the preset from A–D loads on the next clock edge), while /CLR is asynchronous — pulling it LOW forces QA–QD to 0000 immediately, independent of the clock. (The synchronous-clear sibling is the 74LS163.)

The CD4017 is a decade counter with one-hot decoded outputs Q0–Q9: exactly one output is HIGH at a time, advancing on each rising CLK edge while CLKINH is LOW. A HIGH on RESET clears it back to Q0 asynchronously. CO (carry-out) is HIGH for counts 0–4 and LOW for 5–9, giving a divide-by-10 square wave — feed CO into the next chip’s CLK to chain decades. It’s the go-to part for LED chasers and sequencers. Runs on 3–15 V.

The CD4060 is a 14-stage binary ripple counter with a built-in oscillator. Two ways to clock it: drive CLK directly from an external source, or build the on-chip RC oscillator by wiring a resistor Rt from RTC to CLK and a capacitor Ct from CTC to CLK, giving roughly f ≈ 1 / (2.3 × Rt × Ct). The counter advances on the falling edge; a HIGH RESET clears it and stops the oscillator. Not every stage is brought out — the available outputs are Q4–Q10 and Q12–Q14 (the others are internal only), so the earliest tap you can read is Q4, which first goes HIGH after 8 internal clocks. In the simulator keep the oscillator below ~500 Hz (for example Rt = 47 kΩ, Ct = 47 nF ≈ 196 Hz) so the transient solver resolves it cleanly.

Registers, flip-flops, and shift registers

The 74HC74 is two independent D flip-flops. On each rising edge of nCLK, nQ captures the value on nD (and n/Q is its complement). The asynchronous n/PRE (force Q HIGH) and n/CLR (force Q LOW) override the clock — tie both HIGH for normal clocked operation. A flip-flop wired Q̄→D divides its clock by two; string several together for a ripple counter or shift register. Note that asserting /PRE and /CLR LOW at the same time is an undefined state — don’t rely on it.

The 74LS173 is a 4-bit D-type register with tri-state outputs. It latches D1–D4 to Q1–Q4 on the clock when its enable inputs allow, and the output-enable pins (M, N) put the outputs into high-impedance — handy as a write-enabled port onto a shared bus.

Two shift registers expand a microcontroller’s pin count in opposite directions:

• 74HC595 — serial-in, parallel-out, with output latches. Clock data in one bit at a time on SER/SRCLK, then pulse RCLK to latch all 8 bits to QA–QH at once (so the outputs don’t flicker mid-shift). Tie /OE LOW (always enabled) and /SRCLR HIGH. Daisy-chain by feeding QH' into the next chip’s SER. This is the classic “turn 3 pins into 8 outputs” chip.
• 74HC165 — parallel-in, serial-out. Pulse /PL to snapshot 8 parallel inputs D0–D7, then clock them out serially on Q7. The mirror image of the ‘595: read 8 buttons or switches over a few wires.

The 74LS245 is an octal bus transceiver with tri-state outputs in a 20-pin DIP. DIR chooses the direction (A→B or B→A), and /OE HIGH tri-states all eight lines at once. It’s the buffer you drop between a microcontroller and a shared bidirectional data bus.

Decoders and multiplexers

The 74LS157 is a quad 2-to-1 multiplexer. SEL picks the A bank or the B bank through to outputs 1Y–4Y, and /OE enables the chip. Use it to switch a whole nibble between two sources with a single select line.

Two BCD-to-7-segment drivers convert a 4-bit digit (A–D) into the seven segment outputs a–g — but they’re not interchangeable:

The 74LS47 has open-collector active-low outputs that sink current from a common-anode display — put a series resistor (typically 150–470 Ω at 5 V) on each segment; it can sink up to ~24 mA per output. /LT LOW lights every segment for a lamp test. The CD4511 instead has push-pull active-high outputs for a common-cathode display (series resistor per segment to VCC) and adds a latch: LE LOW makes outputs follow the BCD inputs, LE HIGH freezes them. On the CD4511, BCD inputs of 10–15 blank the display rather than showing partial glyphs.

The 74HC138 is a 3-to-8 line decoder/demultiplexer. The three address bits A0–A2 drive exactly one of eight active-LOW outputs (/Y0–/Y7) LOW. The chip is enabled only when /E1 and /E2 are both LOW and E3 is HIGH; otherwise all outputs sit HIGH. It’s the standard chip for address decoding (picking one of eight devices) or for demultiplexing a serial stream.

Memory

The 74LS189 is a tiny 64-bit static RAM organised as 16 words of 4 bits, with inverted tri-state outputs. The 4-bit address A0–A3 selects one of 16 locations; /CS enables the chip and /WE chooses read or write. Data goes in on D1–D4 and reads back inverted on /O1–/O4. It’s a scratchpad for small register files and lookup tables rather than program storage.

For larger, non-volatile storage — programmable lookup tables and microcode — see the parallel EEPROMs on the Memory & EEPROM page (28C16 and 28C256). The astable clock that drives the counters above can be built from the 555 timer or taken from the clock generator.

Example: BCD counter to a 7-segment display

A common build chains a counter into a display driver. The 74LS161 counts 0–15, but the CD4511 only decodes 0–9, so either reset the counter at 10 or limit it to a decade.

clock_gen ── CLK (74LS161)        QA ──── A (CD4511)
   /CLR ── VCC                    QB ──── B
  /LOAD ── VCC                    QC ──── C
    ENP ── VCC                    QD ──── D
    ENT ── VCC
                          LE ── GND   (transparent)
                         /LT ── VCC
                         /BL ── VCC
        CD4511  a–g ── 7× 330 Ω ── common-cathode display ── GND

Tie each chip’s VCC to 5 V, GND to ground, and drop a 100 nF cap across each one. The counter advances on every clock edge; the CD4511 decodes the live count and lights the matching digit.