Memory & EEPROM

de:volt ships two parallel EEPROMs for non-volatile storage and lookup tables: the 28C16 (2K×8, 24-pin DIP) and the 28C256 (32K×8, 28-pin DIP). Both support supply-aware tri-state reads and edge-latched in-circuit writes with a finite write-cycle delay.

A third memory part, the 74LS189 64-bit static RAM, is a logic-family chip and lives on the Logic ICs page rather than here.

How a parallel EEPROM reads

A parallel EEPROM exposes three groups of pins:

Address lines (A0–An): the binary index of the byte you want.
Data lines (I/O0–I/O7): the eight bits of that byte, on the bus.
Control lines: /CE (chip enable), /OE (output enable), and /WE (write enable). All three are active-low: the leading slash marks the inversion.

To read a byte: put the address on A0–An, hold /WE high, then pull /CE low and /OE low. The chip places the stored byte onto I/O0–I/O7. The read is combinational in this model, with no access-time delay. Deassert /OE or /CE and the I/O pins return to high impedance, releasing the bus.

Both parts read at the supply levels you’d expect from a CMOS-EEPROM family:

Property	Value
Logic family	CMOS-EEPROM
VCC range (min / nom / max)	4.5 / 5 / 5.5 V
Input low max (`v_il_max`)	0.8 V
Input high min (`v_ih_min`)	2 V
Output current max (`io_max`)	4 mA

Use Load .bin in the Inspector to seed the contents image. An erased or empty image reads as 0xFF. Bus writes made while the simulation runs update the image in memory, and that live image is saved with the project. Loading a different .bin image reseeds the device.

How an in-circuit write works

Set the address and data bus with /OE high. The model accepts either of the common write-latch forms:

Pulse /WE low while /CE stays low; address and data latch on /WE rising.
Hold /WE low and pulse /CE; address and data latch on /CE rising.

An accepted byte takes 10 ms of simulated time to commit. While that address is busy, I/O7 presents the inverse of the pending bit 7 and I/O6 toggles on successive reads, providing the supported data-polling behaviour. Unrelated addresses remain readable. Write state, including a pending cycle, participates in simulation snapshot/rollback so a rejected solver step cannot commit memory early.

The 28C16 accepts ordinary writes. The 28C256 enables software data protection by default: an unsequenced write is ignored until the standard 0x5555/AA, 0x2AAA/55, 0x5555/A0 unlock sequence is completed. Advanced circuits can set sdpBypass = 1 to bypass this teaching model of protection.

28C16: 2K×8 EEPROM (`ic-28c16`)

2,048 bytes addressed by 11 lines (A0–A10), eight data lines, in a 24-pin DIP. The classic use is a lookup table: for example a binary-to-7-segment decoder when a CD4511 isn’t on hand, or any small combinational function you’d rather store than build from gates.

Pinout

24-pin DIP. Pin 1 is at the notch end; count counter-clockwise.

Pin	Label	Function	Pin	Label	Function
1	A7	Address	24	VCC	+5 V supply
2	A6	Address	23	A8	Address
3	A5	Address	22	A9	Address
4	A4	Address	21	/WE	Write enable (active-low)
5	A3	Address	20	/OE	Output enable (active-low)
6	A2	Address	19	A10	Address
7	A1	Address	18	/CE	Chip enable (active-low)
8	A0	Address	17	I/O7	Data
9	I/O0	Data	16	I/O6	Data
10	I/O1	Data	15	I/O5	Data
11	I/O2	Data	14	I/O4	Data
12	GND	Ground	13	I/O3	Data

Read sequence

Address  A0–A10 ──── (set the byte index)
/CE  ── LOW ──┐
/OE  ── LOW ──┴──→ I/O0–I/O7 drive the stored byte
/WE  ── HIGH ──── (read mode; not writing)

Hold /WE high during reads. With /CE or /OE released, the I/O bus floats so several devices can share it.

28C256: 32K×8 EEPROM (`ic-28c256`)

The same read/write model with 16× the storage: 32,768 bytes addressed by 15 lines (A0–A14), in a 28-pin DIP. Use it when a 28C16’s 2K is not enough for larger character tables, microcode, or a sizeable memory image.

Pinout

28-pin DIP. The extra four pins over the 28C16 carry the higher address lines (A11–A14).

Pin	Label	Function	Pin	Label	Function
1	A14	Address	28	VCC	+5 V supply
2	A12	Address	27	/WE	Write enable (active-low)
3	A7	Address	26	A13	Address
4	A6	Address	25	A8	Address
5	A5	Address	24	A9	Address
6	A4	Address	23	A11	Address
7	A3	Address	22	/OE	Output enable (active-low)
8	A2	Address	21	A10	Address
9	A1	Address	20	/CE	Chip enable (active-low)
10	A0	Address	19	I/O7	Data
11	I/O0	Data	18	I/O6	Data
12	I/O1	Data	17	I/O5	Data
13	I/O2	Data	16	I/O4	Data
14	GND	Ground	15	I/O3	Data

Reads work exactly as on the 28C16: assert /CE and /OE low, hold /WE high, and the byte at A0–A14 appears on I/O0–I/O7.

Simulator behaviour

Reads are combinational: the data bus reflects the addressed byte directly, with no access-time delay and no clock.
The control lines are active-low. A read needs /CE low and /OE low; releasing either tristates the I/O bus.
Writes latch on the supported /WE or /CE edge, commit after 10 ms, and expose I/O7/I/O6 data polling while busy.
The 28C256 models its three-write software-protection unlock; the 28C16 does not require it.
Bytes written during simulation survive ordinary reloads and are saved with the project. Loading another .bin deliberately replaces the live image.
Cell programming physics, endurance, retention aging, partial-write corruption, supply-ramp sensitivity, access-time and pin-timing margins, temperature effects, and package timing skew are not modelled.
For a small read/write scratchpad instead of a fixed table, see the 74LS189 on the Logic ICs page.

Select an EEPROM to see the Included / Not included model disclosure. A successful simulated write proves the supported bus sequence and timing model, not long-term memory reliability.

555 Timer Motor Drivers

Memory & EEPROM

How a parallel EEPROM reads

How an in-circuit write works

28C16: 2K×8 EEPROM (ic-28c16)

Pinout

Read sequence

28C256: 32K×8 EEPROM (ic-28c256)

Pinout

Simulator behaviour

28C16: 2K×8 EEPROM (`ic-28c16`)

28C256: 32K×8 EEPROM (`ic-28c256`)