Oscilloscope, Multimeter & Analysis
de:volt has two instrument surfaces. Open the Meter from the editor toolbar, and open the Analysis panel along the bottom of the editor for the oscilloscope and analysis workbench. The oscilloscope is free; logic analysis, captures, measurements, cursors, operating point, and sweeps require Pro.
The scope and meter are ideal observers. They do not add probe resistance or capacitance, ammeter burden, a meter fuse, or an ohms-test current to the circuit. Add an explicit component when that loading matters, and verify hardware with a real instrument.
Multimeter
Choose Meter in the toolbar to show the floating two-probe meter. Drag the red and black tips to component pins or breadboard holes; a snapped tip follows that electrical node while you pan or zoom. The black probe starts on Ground when a ground hole is available. Probe controls and dial positions are keyboard operable, and HOLD freezes the displayed reading.
Dial modes
| Mode | What the simulator reports |
|---|---|
| AUTO | Continuity when both probes are on one node; otherwise DC voltage |
| V | V(red) − V(black) from the last valid solved state |
| Ω | Equivalent resistance of the plain-resistor network between the probes |
| A | Signed solved current only when the probes straddle one unambiguous two-terminal branch |
The meter distinguishes three different outcomes:
- A numeric value is available from the current or paused solved state.
OLin resistance mode means no supported resistive path connects the probes.---means a voltage/current value is unavailable or current direction cannot be identified. It is not treated as zero or as an over-range reading.
Resistance mode solves series and parallel networks of ordinary resistor parts, excludes resistors that have failed open, and treats sources and every other component as open. A real ohmmeter must be used on a de-energised circuit; this simulator calculation is a topology observer and does not inject a physical test current. Continuity sounds below 50 Ω.
Current mode does not insert the meter in series. It can report a branch only when exactly one two-terminal component spans the two probe nets and its exact identity-matched telemetry provides a meaningful signed current. Package totals, multi-channel aggregates, stale pre-solve data, and ambiguous parallel branches display ---.
Oscilloscope
Open the Analysis panel and stay on the Scope tab. The scope plots node voltages over simulated time.
- Tick channels in the left list. The row value is the raw solved node voltage; the plotted trace applies the selected coupling and ADC model.
- Choose a time window and vertical range. Auto changes plot scaling but still uses a declared ±30 V ADC input span.
- Choose DC or AC coupling for each channel.
- Pause freezes acquisition while the circuit simulation continues; Clear removes trace history.
- Roll and trigger modes provide rising/falling edge, level, source, position, auto/normal/single behaviour, and optional persistence.
Sampling and bandwidth
Scope and logic samples are captured inside the worker integration loop, not at the browser’s display refresh rate. The scope requests roughly 10,000 points per visible window, bounded from 100 Sa/s to 10 kSa/s.
The output timestamps form a uniform grid. A grid point between two accepted solver states uses linear dense interpolation; it is not another independent circuit solve. The displayed effective sample rate is conservatively capped by the coarsest accepted solver interval in the acquisition. The UI derives Nyquist from that effective rate, not from the denser output grid.
Use the rate, Nyquist, valid-sample count, and coverage status shown above the plot when judging a measurement. Source and firmware events are step-aligned where supported, but pause/resume, invalid solves, or unavailable data remain explicit gaps. Traces and timing calculations never draw or measure across a gap as though it were observed.
Scope input model
The scope transforms a separate copy of the clean solved samples in this order:
- Per-channel input coupling.
- Saturating 12-bit ADC quantisation over the selected input range.
DC coupling passes the solved level. AC coupling is a first-order high-pass with a 100 ms time constant (about 1.59 Hz corner). After a reset or gap, it establishes a new local baseline without inventing an unseen switch-on transient. The status row shows the selected input span and volts per ADC code.
Display noise is optional, deterministic front-end decoration at a fixed declared density and bandwidth. It changes only the drawn trace. It is excluded from measurements, cursors, captures, and exported samples. The simulator does not generate circuit Johnson, shot, flicker, hum, or environmental pickup noise.
The input model omits physical probe loading, anti-alias filtering, analogue clipping/recovery detail, calibration drift, full ADC INL/DNL, and circuit-derived broadband noise.
Measurements and cursors
Pro adds minimum, maximum, mean, RMS, frequency, period, duty cycle, and a pair of cursors. These tools read the same coupled and quantised instrument-domain samples shown on the plot, before optional display noise.
Amplitude statistics use every finite displayed sample. Frequency, period, and duty use only the longest contiguous finite segment so a gap cannot create a false period. The estimator uses robust midpoint crossings, hysteresis, and interval-consistency checks; when it lacks enough cycles or samples, it leaves timing unavailable and marks coverage as limited or insufficient. A coverage badge rates numerical evidence only, not component-model accuracy.
Pause first when placing precise cursors. Cursors cannot recover information above the declared acquisition bandwidth.
Nodes and channels
Every junction in the circuit, meaning each set of holes and legs that are electrically joined, is a node. The app labels nodes Node 0, Node 1, Node 2, … (internally n0, n1, n2, …), and the 0 V reference is Ground (internally gnd). Each node has a stable colour shared by its scope swatch, trace, and diagram highlight.
Highlighting nodes on the diagram
Open View → Node highlighting and choose:
- Off: the default view.
- On hover: hovering a wire, breadboard hole, component pin, supply terminal, or jumper highlights every visible point on the same node and outlines its scope channel.
- Show all nodes: draws every visible node and label at once. Pan or zoom to reveal more. This temporary view is included in a PNG export while enabled.
Highlighting reads wiring topology and works even when the simulation is stopped or the circuit is incomplete.
Channel limits
| Plan | Scope channels |
|---|---|
| Signed out / Hobby | 4 |
| Pro | 16 |
At the limit, remaining channel checkboxes are disabled until you remove one. A differential probe (netA − netB) counts as one channel.
Analysis workbench (Pro)
Captures
Save the currently visible instrument-domain trace to compare with later runs. Captures remain in the session, up to twelve at a time, and can be included in a PDF project report.
A new capture records its physics-model version, circuit revision, environment, requested/effective sample rates, Nyquist limit, sample count, time window, trigger state, coupling, ADC range and resolution, solver validity, and whether display noise was enabled. Display noise is never mixed into stored samples. JSON export preserves the waveform and this provenance together.
Logic analyzer
The Logic tab shows up to eight selected nodes as sampled digital lanes. It uses the same effective-rate and explicit-gap acquisition contract as the scope, and warns when a pulse spans fewer than four samples or a period fewer than ten.
Auto thresholding examines exact catalog identities on receiver input pins. When one receiver family applies, the midpoint of its declared VIL/VIH envelope is used and the undefined band is disclosed. Mixed receiver families or stale identities require a manual threshold instead of selecting a family arbitrarily. With no declared receiver, the fallback is 2.5 V.
The display is two-state at the selected threshold. It does not model probabilistic receiver behaviour, metastability, or a third digital state inside the VIL-to-VIH indeterminate region.
Operating point
The Operating point tab takes a one-shot snapshot of available solved net voltages and component telemetry. Exact identity-matched structured telemetry supplies current direction and power when those meanings are unambiguous. Multi-channel totals are labelled as aggregates; power is omitted when terminal voltage and signed current do not share a trustworthy reference. Missing values display Unavailable, never a fabricated zero.
The snapshot records simulation time and convergence state. Treat a non-converged warning as invalid physical evidence. CSV export preserves the available values and their meanings.
Sweeps
The Sweeps tab runs parameter studies in the background with progress and cancellation:
- DC sweep steps a source parameter and plots selected node responses.
- Temperature sweep changes the declared ambient temperature.
- Frequency response (AC / Bode) offers two methods. The default fast small-signal method linearises the circuit about its DC operating point and solves the complex system directly. The sine sweep method instead drives a real sine at each frequency and extracts magnitude/phase with a single-bin DFT.
- Monte Carlo performs seeded runs using supported component tolerances.
Every analysis step checks solver convergence. A failed point is rolled back and rejected rather than being included as plausible data. Exact catalog identities are preserved across analysis clones.
The two AC methods answer different questions. The small-signal linearised method is exact for linear circuits and near-instant, but being a linearisation it cannot show clipping, slew or any large-signal effect; points sitting on a near-singularity (such as an ideal lossless LC at exact resonance) are solved through a regularisation and flagged. It is unavailable when a microcontroller is present, because running firmware has no small-signal model. The sine sweep is not a linearisation, so its nonlinear results depend on the configured drive amplitude and source resistance, and high-Q points can be marked not settled when the fixed settling window is too short. Neither is a SPICE .ac engine; both are teaching-grade. Monte Carlo covers only the tolerances explicitly wired into that analysis; it is not a vendor process-corner or lifetime model.
These analyses are teaching-grade tools inside the declared component-model envelopes. Passing a sweep or capture is not production sign-off. Verify important designs against the selected datasheets, a higher-fidelity model where needed, and real measurements.
Signal sources
The signal sources provide sine, square, pulse, triangle, ramp, PWL, and deterministic noise stimulus. The general Signal Generator has finite source resistance; the dedicated Pulse and Clock generators are ideal voltage sources. Their exact assumptions are listed on Power & Signal Sources.