555 Timer

The 555 is the classic timing IC: a comparator pair, a flip-flop, and a discharge transistor in a DIP-8 package that, with a couple of resistors and a capacitor, becomes either a free-running oscillator or a one-shot pulse generator. de:volt ships the NE555 (ne555), modelled in both astable (oscillator) and monostable (one-shot) configurations.

Specs

Property	Value
Supply range (`vcc_range`)	4.5 V min / 5 V nominal / 16 V max
Max output current (`io_max`)	0.2 A (200 mA)
Package	DIP-8

The output (pin 3) is a stout push-pull stage that swings near rail-to-rail and can source or sink up to 200 mA — enough to drive an LED or a small load directly.

Pinout

Pin	Label	Function
1	GND	Ground
2	TRIG	Trigger — fires when pulled below 1/3 VCC
3	OUT	Output (near rail-to-rail)
4	RST	Reset — active LOW; tie to VCC to disable
5	CTL	Control voltage — sets the comparator threshold
6	THR	Threshold — resets the cycle at 2/3 VCC
7	DIS	Discharge — open-collector, drains the timing cap
8	VCC	Positive supply (4.5–16 V)

Pin 1 (GND) is at the notch/dot end. Place the DIP with the notch facing left, pin 1 at the bottom-left, and count counter-clockwise. A DIP socket is recommended.

Astable — free-running oscillator

In astable mode the 555 oscillates on its own, charging the timing capacitor through Ra + Rb and discharging it through Rb alone. That asymmetry is why the standard astable spends longer HIGH than LOW.

Wire it up as follows:

Tie pins 2 (TRIG) and 6 (THR) together at the timing capacitor — the same node feeds both comparators.
Resistor Ra from VCC to pin 7 (DIS).
Resistor Rb from pin 7 (DIS) to the pin 2/6 node.
Timing capacitor C from the pin 2/6 node to GND.
Pin 4 (RST) to VCC, so the chip never resets mid-cycle.
100 nF from pin 5 (CTL) to GND for noise immunity.

The timing then follows:

f    ≈ 1.44 / ((Ra + 2·Rb)·C)
duty = (Ra + Rb) / (Ra + 2·Rb)

Because the charge path is Ra + Rb and the discharge path is only Rb, the duty cycle is always above 50% with plain resistors — making Rb much larger than Ra drives it toward (but never reaches) 50%.

Example: astable

        VCC (5 V) ──┬──────────────┬──── pin 8 (VCC)
                    Ra           pin 4 (RST)
                     │
        pin 7 (DIS) ─┤
                    Rb
                     │
   pins 2,6 ─────────┴──┬──── (timing node)
                        C
                       GND

   pin 3 (OUT) ──── square wave out
   pin 5 (CTL) ──── 100 nF ──── GND
   pin 1 (GND) ──── GND

Monostable — one-shot

In monostable mode the 555 sits idle until you trigger it. A falling edge on pin 2 (TRIG) below 1/3 VCC fires a single output pulse, after which the chip waits for the next trigger. A single resistor R from VCC to pins 6/7 and a capacitor C from pins 6/7 to GND set the pulse width:

t ≈ 1.1·R·C

The output stays HIGH for that interval, then returns LOW until triggered again. This is the standard way to stretch a brief input into a fixed-length pulse — a debounced button press, a timed relay pulse, or a delay.

Cross-links and templates

A finished 555 LED blinker is one of de:volt’s starter templates — load it to see the astable wiring above oscillating an LED, then tweak Ra, Rb, and C to change the rate. For driving digital logic from the 555’s square-wave output, see Logic ICs.

New to placing and wiring parts? Start with Getting started.

Logic ICs Memory & EEPROM