de:volt LearnTeacher packsLogic Gates

Teacher pack: Logic Gates

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Master digital logic from HIGH/LOW signals through AND, OR, NOT, NAND, XOR gates to a working half-adder — all with real 74LS ICs.

  • Lessons: 8
  • Total lesson time: 175 minutes (about 2 h 55 min)
  • Level: intermediate
  • Objectives to mark: 43
  • Access: every lesson needs Pro or a school licence

Lesson sequence

#LessonMinutesChecksParts
1Digital HIGH and LOW104breadboard, bench supply, battery pack, SPDT switch, resistor
2The NOT Gate154breadboard, bench supply, battery pack, 74LS04 NOT IC, resistor, LED, dip switch, SPDT switch
3The AND Gate206breadboard, bench supply, battery pack, 74LS08 AND IC, resistor, LED, dip switch, SPDT switch
4The OR Gate206breadboard, bench supply, battery pack, 74LS32 OR IC, resistor, LED, dip switch, SPDT switch
5NAND: The Universal Gate256breadboard, bench supply, battery pack, 74LS00 NAND IC, resistor, LED, dip switch, SPDT switch
6The XOR Gate206breadboard, bench supply, battery pack, 74LS86 XOR IC, resistor, LED, dip switch, SPDT switch
7Capstone: Half-Adder307breadboard, bench supply, battery pack, 74LS86 XOR IC, 74LS08 AND IC, resistor, LED, dip switch, SPDT switch
8Bonus: NAND Latch (Memory)354breadboard, bench supply, battery pack, 74LS00 NAND IC, resistor, LED, dip switch, SPDT switch
Total17543

Allow 175 minutes (about 2 h 55 min) of build time across 8 lessons. The estimates assume a learner working alone at the board; a class discussion, a demonstration and a pack-away typically add a third on top.

Curriculum mapping

The last two columns are deliberately blank. Fill in your own syllabus codes and the outcome each lesson evidences, then keep this page with your scheme of work.

#LessonFocusYour codeYour outcome
1Digital HIGH and LOWDiscover what HIGH and LOW mean in digital logic and measure the voltage levels that define each state.
2The NOT GateBuild your first logic gate circuit using the 74LS04 hex inverter and verify the NOT truth table.
3The AND GateBuild the AND gate truth table using all four gates of a 74LS08, proving every input combination in one steady-state circuit.
4The OR GateBuild the OR gate truth table using all four gates of a 74LS32 and discover why OR outputs HIGH for almost every input combination.
5NAND: The Universal GateExplore the NAND gate’s truth table with a 74LS00, then prove its universality by wiring it as a NOT gate using tied inputs.
6The XOR GateBuild the XOR gate truth table with a 74LS86 and discover the exclusive-OR rule: output is HIGH only when inputs differ.
7Capstone: Half-AdderCombine a 74LS86 XOR and a 74LS08 AND gate to build a working 1-bit half-adder — the simplest binary arithmetic circuit.
8Bonus: NAND Latch (Memory)Build a bistable SR latch from two cross-coupled 74LS00 NAND gates and observe how logic circuits can hold a state — the hardware basis of memory.

Objective checklist

One line per automatically-marked objective, in the order a learner meets them. Learners tick their own as they pass; a teacher can use the same list to mark a paper submission or to spot the lesson a class is stuck on.

1. Digital HIGH and LOW

  • Connect the 5V supply to the breadboard power rails.
  • Place at least one SPDT switch on the bench.
  • Create a digital HIGH signal (≥ 4.0 V) on an SPDT switch’s COM pin.
  • Create a digital LOW signal (≤ 0.8 V) on a second SPDT switch’s COM pin.

2. The NOT Gate

  • Place a 74LS04 NOT gate IC on the bench.
  • Drive gate 1 of the first 74LS04 with a LOW input — the output (1Y) must be HIGH (≥ 4.0 V).
  • Drive gate 1 of the second 74LS04 with a HIGH input — the output (1Y) must be LOW (≤ 0.8 V).
  • Attach an LED (with a ≥ 330 Ω series resistor) to the HIGH output and light it up.

3. The AND Gate

  • Place a 74LS08 AND gate IC with Vcc and GND connected.
  • Gate 1 (inputs 0,0): 1Y must be LOW (≤ 0.8 V).
  • Gate 2 (inputs 1,0): 2Y must be LOW (≤ 0.8 V).
  • Gate 3 (inputs 0,1): 3Y must be LOW (≤ 0.8 V).
  • Gate 4 (inputs 1,1): 4Y must be HIGH (≥ 4.0 V) — the only true AND output.
  • Attach an LED to the gate-4 output to visually confirm the only HIGH result.

4. The OR Gate

  • Place a 74LS32 OR gate IC with Vcc and GND connected.
  • Gate 1 (inputs 0,0): 1Y must be LOW (≤ 0.8 V) — the only combination that produces LOW for OR.
  • Gate 2 (inputs 1,0): 2Y must be HIGH (≥ 4.0 V).
  • Gate 3 (inputs 0,1): 3Y must be HIGH (≥ 4.0 V).
  • Gate 4 (inputs 1,1): 4Y must be HIGH (≥ 4.0 V).
  • Attach an LED to any HIGH output to visually confirm OR’s dominant HIGH behaviour.

5. NAND: The Universal Gate

  • Place a 74LS00 NAND gate IC with Vcc and GND connected.
  • Gate 1 (inputs 1,1): 1Y must be LOW (≤ 0.8 V) — NAND’s only false output.
  • Gate 2 (inputs 0,0): 2Y must be HIGH (≥ 4.0 V).
  • Universality proof: a NAND gate with BOTH inputs tied HIGH outputs LOW (≤ 0.8 V) — it acts as a NOT gate.
  • Universality proof: a NAND gate with BOTH inputs tied LOW outputs HIGH (≥ 4.0 V) — it acts as a NOT gate.
  • Attach an LED to the gate-4 (tied-LOW) output to confirm the NAND-as-NOT HIGH output.

6. The XOR Gate

  • Place a 74LS86 XOR gate IC with Vcc and GND connected.
  • Gate 1 (inputs 0,0): 1Y must be LOW (≤ 0.8 V) — same inputs produce LOW.
  • Gate 2 (inputs 1,0): 2Y must be HIGH (≥ 4.0 V) — different inputs produce HIGH.
  • Gate 3 (inputs 0,1): 3Y must be HIGH (≥ 4.0 V) — different inputs produce HIGH.
  • Gate 4 (inputs 1,1): 4Y must be LOW (≤ 0.8 V) — same inputs produce LOW (unlike OR).
  • Attach an LED to gate-2’s HIGH output (inputs differ) to confirm XOR’s ‘different-inputs’ behaviour.

7. Capstone: Half-Adder

  • Place both a 74LS86 (XOR) and a 74LS08 (AND) IC on the bench with Vcc and GND connected.
  • 0 + 0: Sum (XOR gate 1, pin 1Y) must be LOW (≤ 0.8 V) and Carry (AND gate 1, pin 1Y) must be LOW (≤ 0.8 V).
  • 1 + 0: Sum (XOR 2Y) must be HIGH (≥ 4.0 V); Carry (AND 2Y) must be LOW (≤ 0.8 V).
  • 0 + 1: Sum (XOR 3Y) must be HIGH (≥ 4.0 V); Carry (AND 3Y) must be LOW (≤ 0.8 V).
  • 1 + 1: Sum (XOR 4Y) must be LOW (≤ 0.8 V); Carry (AND 4Y) must be HIGH (≥ 4.0 V).
  • Attach an LED (with ≥ 330 Ω resistor) to the Sum output (XOR gate 2, 1+0 case) to show when Sum is HIGH.
  • Attach an LED (with ≥ 330 Ω resistor) to the Carry output (AND gate 4, 1+1 case) to show when Carry is HIGH.

8. Bonus: NAND Latch (Memory)

  • Place a 74LS00 NAND IC on the bench with Vcc and GND connected.
  • Assert SET (drive Set_n LOW, Reset_n HIGH): Q output (gate-1 output 1Y) must go HIGH (≥ 4.0 V).
  • Assert RESET (drive Reset_n LOW, Set_n HIGH): Q output (1Y) must go LOW (≤ 0.8 V).
  • HOLD: release both inputs HIGH (Set_n=HIGH, Reset_n=HIGH after SET) — Q must STAY HIGH (≥ 4.0 V).
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